This application claims priority to Japanese Patent Application No. 2001-229043 filed on Jul. 30, 2001.
1. Field of the Invention
The present invention relates to a data processor such as a microprocessor, and more specifically, the present invention relates to an information processor capable of improved memory access speed and reduced operating power consumption.
2. Description of the Background
One of the main operations of processors is to gain access to a memory designated by an address and to read data of the memory. These functions encompass a significant factor in determining the performance of a processor. In general, the sum of values of two registers in a processor is used as the memory access address. The values obtained by accessing the memory are then stored in the registers, and the xe2x80x9cregistered valuesxe2x80x9d (i.e., the values of the data in the registers) are used to calculate an address for the next memory access. Accordingly, the ability to repeat these functions: addition; access; and registration, is a main factor in the performance of the processor. Because the route from an accessed memory to the registers can be concealed by controlling a bypass from the accessed memory to the adder, the processing speed of the repetition of addition to calculate an address and access to a memory determines the performance of the processor.
Many of the recent processors are provided with a cache memory or a translation lookaside buffer (TLB) to raise the memory-accessing speed. A cache memory is a high-speed memory used to store part of the data in the main memory. The TLB is a high-speed memory used to store part of the data for address translation and memory protection information. In either case, the memory-accessing operation is governed by addresses generated by the operation of the addition mentioned above.
Some processors, which require high-performance memories, are provided with various memories such as memories for users"" free use and memories specializing in the processing of digital signals in addition to cache memories and TLBs. These memories are arranged in an address space in each processor. A program gains access to a memory by means of an address indicating the specific space of a type of memory. In other words, the given address determines to which memory access should be made. In some high-speed processors, all of the types of memories are activated immediately after the addition for a memory-designating address, without waiting for the identification of the type of the memory in question, and data is thereafter read from only one relevant memory.
Japanese Patent Laid-open JP-A-76648/1992 discloses a method for quickly accessing a cache memory when the sum of values of two registers is used as a memory address. This method takes advantage of the fact that an entry address of a cache memory is determined by adding partial bits of the calculated address, and the method provides for access to such a memory by reading two successive entries, without waiting for the carry from addition of the lower bits, but by assuming the two cases in which the carry is xe2x80x9c0xe2x80x9d and xe2x80x9c1.xe2x80x9d
There are at least two main problems with these conventional methods. The first problem is electric power consumption. If all the memories of a processor with various types of memories are operated to increase the accessing speed, excess power is consumed. A requirement for a reduction in the power consumption of processors for battery-driven mobile equipment in particular has been increasing. Likewise, desktop equipment requires the reduction in the quantity of heat generated by the LSI as clock frequencies of processors increase. The power consumption can be reduced by determining the relevant memory type after calculating the memory-designating address, but this approach does not meet the requirement for high memory access speed.
The second problem is involved in the approach of JP-A-76648/1992. This approach raises the memory-accessing speed but cannot flexibly be applied to TLBs. To avoid a conflict of TLB entries under a plurality of processes, the results of addition are often hash processed by an address space identifier (ASID) and then used as entry addresses. An Exclusive OR (XOR) for each bit is often used in hash processing. In this case, two entry addresses do not necessarily turn out to be successive. A specific example will be described below, assuming that the entry addresses of a TLB are five bits long, an entry address obtained by addition is xe2x80x9c00001xe2x80x9d, and appointed ASIDs are xe2x80x9c00000xe2x80x9d and xe2x80x9c00001.xe2x80x9d
It is assumed in the conventional method disclosed in JP-A-76648/1992 that the entry address without carry and the entry address with carry turn out to be successive; therefore, this approach cannot be applied to the TLB of which the above entry addresses are hash processed. Additionally, it is suggested in the drawings of JP-A-76648/1992 to read out two pieces of data from a single memory mat. Accordingly, it is necessary to use a dual-port-type memory with a specialized address decoder. The area of the memory, therefore, increases, and the xe2x80x9cspecialtyxe2x80x9d nature of the memory confines its application to a relatively narrow range of products.
In at least one embodiment, the present invention preferably provides a data processor capable of operating with reduced power consumption level compared to convention processors without reducing its memory-accessing speed. The present invention may also provide a technology for increased access speed to memories which is applicable to TLBs.
In at least one embodiment, the invention provides a data processor comprising: (i) an adder which adds a base address and an offset; (ii) xe2x80x9cNxe2x80x9d memories (wherein N is a natural number) whose entry address is constituted by partial bits of the resultant address of said addition by the adder; (iii) a partial bit adder which adds partial bits of the base address and partial bits of the offset corresponding to said partial bits of the base address; (iv) a decision logic circuit connected to the partial bits adder that selects and activates no more than xe2x80x9cNxe2x88x921xe2x80x9d memories; and (v) a multiplexor which selects one of the outputs of the activated memories.
The data processor preferably takes advantage of the fact that the different types of memories can be distinguished based only on partial bits of an address obtained by a base address and an offset. The data processor has, in addition to an adder for memory addresses, a partial bit adder to calculate partial bits of the address to distinguish between the different types of memories. Because the partial addition does not take into account the possible carry from the lower bits, two types of memories (at most) are both operated in case the carry should be xe2x80x9c1xe2x80x9d and in case it should be xe2x80x9c0.xe2x80x9d Because the partial bit adder operates at a high speed, the decision logic circuit can preferably identify two relevant types among many types of memories on the LSI before the adder generates a memory address.
According to another embodiment of the present invention, there is provided a data processor comprising: (i) a first partial bit adder which adds a part of a base address, a part of an offset, and the logical sum of said part of the base address and said part of the offset; (ii) a second partial bit adder which adds a part of a base address, a part of an offset, and the logical product of said part of the base address and said part of the offset; (iii) a first memory bank which is connected to the first partial bit adder; (iv) a second memory bank which is connected to the second partial bit adder; and (v) a multiplexor which is connected to the first and second memory banks and which selects data from the first memory bank or data from the second memory bank in accordance with the resultant value of addition of the base address and the offset.
By applying the above approach to the entry addresses of memories and using a partial bit adder to add a part of the base address and a corresponding part of the offset, two relevant entry addresses can be identified. Moreover, access to TLBs can be addressed by providing an even-entry-number memory bank and an odd-entry-number memory bank, each bank including an exclusive partial bit adder, and performing control so that a proper value of carry will be input into each of the partial bit adders in order to gain access to the appropriate memory bank.